We are seeking skilled engineers for designing high-performance Virtualization and Interconnect Architecture and developing RTL for both Automotive and High-Performance Computing. Roles: 1. Develop, assess, and refine RTL to achieve performance, power, area, and timing goals. 2. Develop micro-architecture by exploring early high-level macro architectures, researching micro-architecture, and defining detailed specifications. 3. Coordinate co-design efforts between architecture, software, and hardware teams to achieve functional realization. 4. Develop and implement interconnect methodologies, such as simulation, emulation, implementation, and efficiency improvement. 職缺需求 1. MS or PhD degree in electrical engineering or equivalent experience. 2. At least 4+ years of IC design experience. 3. Good understanding of System on Chip (SOC) design and verification concepts, including the design flow from specification to tape-out. 4. At least 8+ years of experience in digital IC design or proficient in SystemC/C++ (preferred). 5. Expertise in one or more of the following: Interconnect, Virtualization, Access control, MMU, Security, IO technologies, Multimedia accelerator, Platform integration (preferred). 6. Proficient in scripting languages such as Perl, Python, and TCL (preferred). 7. Embrace challenges.
1. Develop high speed interface subsystem architecture and integrate PCIe, MIPI, or DisplayPort subsystem. 2. Develop security and FuSa function on PCIe, MIPI, or DisplayPor degital circuit. 職缺需求 1. Master degree in electrical engineering or equivalent practical experience. 2. At least 5 years of experience in digital IC design. 3. Familiar with digital design and integration flow. 4. Experience of SOC architecture design is a plus 5. Experience in the design of MIPI interfaces, DisplayPort and HDMI is a plus 6. Experience in the design of FuSa and cybersecurity-related circuit is a plus.
1. Implement and maintain device drivers, or firmware for high-speed interfaces, such as PCI Express, MIPI CSI-2, USB or UFS. 2. Develop FuSa and security software framework for high-speed interfaces to fulfill automotive requirements. 職缺需求 1. Master's degree in Computer Science, Electrical Engineering, other technical field 2. Experience with C++, C. 3. Experience in Linux kernel development and device driver performance optimization 4. Experience with software for embedded systems in automotive electronics. 5. Experience with automotive standards such as ISO26262
1. Architecture design and RTL implementation of Smartphone chipset 2. Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis 職缺需求 1. Familiar with digital IC design, DFT, and FPGA emulation flow 2. Experienced in SoC architecture, Embedded Processor (DSP/MCU), and bus (ARM bus) system architecture design is a plus 3. Experienced in chip integration is a plus 4. Experience with External Memory Interface design is a plus 5. Experience with system verification job is a plus 6. Experience with security hardware design is a plus 7. Experience with DRAM bandwidth improvement is a plus 8. Experience with analog/digital interface design is a plus
1. Develop scalable platform clocking architecture for automotive SoC 2. Enhance SoC clock architecture and technology development to address the automotive SoC requirements 3. Drive clock architecture and designs to optimize power, performance, and implementation, including physical design and timing closure 職缺需求 1. Proven experience in developing clock architecture for automotive SoC 2. Knowledge of the automotive requirements and standards (e.g. ISO26262) 3. Familiar with clocking designs for safety, security 4. Expertise in digital IC design implementation flow, clock tree implmentation, timing closure, power optimization, SoC architecture 5. Ability to improve the technology and designs for SoC clocking 6. knowing automotive sign-off, project development, or chip integration flow is a plus
We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement. 職缺需求 Required Industry Experience: • Minimum of 3+ years of proven experience in DFT/DFM, particularly in automotive ADAS SoC chip design . • Familiarity with automotive-specific quality and reliability standards, such as function safety ISO26262 and AEC-Q100. • Experience in (automotive) semiconductor manufacturing process, reliability, and yield improvement. Key Technology Skills: • Strong knowledge of SCAN, MBIST, BIST...DFT design structure and test coverage enhancement. • Strong knowledge of manufacture(DFM) yield improvement, test time reduction, test cost reduction. • Knowledge of SoC design tools and methodologies, including synthesis, static timing analysis, and formal verification. • Skilled in RTL coding and scripting languages, such as TCL/Perl/Python. Nice to have: • Strong knowledge of automated testing equipment (ATE) and test program development. • Expertise in EDA tools for DFT analysis, such as Mentor Graphics Tessent or Synopsys DFTMAX, Tessent MBIST, automotive LBIST. • Expertise in ATPG pattern generation and coverage analysis, specifically for automotive SoC chip design. • Experience in high performance and low power design methodologies.
IC package & PCB electromagnetic model extraction 職缺需求 Designing complex layout for mixed signal, and analog/rf circuits in deep sub-micron CMOS technologies. Reviewing and analyzing floorplans and complex circuits with circuit designers. Running complete set of design verification tools available on Analog/RF blocks. Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. Exceeding engineering specifications and expectations by working closely with the circuit design team. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
1. 數位 IC 設計 2. 高速 Ethernet PCS/RSFEC/MAC 設計 3. 高速電路架構與整合 職缺需求 1. 兩年以上相關工作經歷 2. 熟數位 IC 設計 3. 熟數位 IC 設計流程 4. 有數位 IC 架構設計能力為佳 5. 熟高速電路與低功耗設計
Work in Analog/Mixed-Signal Design Verification Methodology Development group to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows, and work hands-on with AMS IP Teams for AMS DV flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with digital design, analog design, analog behavioral modeling and design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to establish and maintain Verification Platform to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products. • Work in methodology development team to establish, streamline and enhance new and existing AMS DV related development method, coding process and integration flows. • Work with teams to enable deployment of new flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as SERDES, etc) and integration. • Document on new flows and processes for AMS DV. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA 職缺需求 • Quick learner with strong critical thinking and creative problem-solving skills. • Solid knowledge in ASIC design process, computer architecture, digital design and UVM-based design verification methodologies. • Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA). • Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc. • Proficient on Design Verification development process, from specification to test plan, to configurable test bench, drivers and checkers setup, to test suite building to meet functional and code coverage goals, and power-aware simulations and gate level simulations. • 5+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal cores and/or chips. • Familiar with programming languages: C, C++, and/or SystemC. • Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus. • Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus • Design or Verification work experience on Wireless and/or Wired Interface Standards, such as WiFi and SERDES, etc., is a plus.
Work in Analog/Mixed-Signal Modeling and Verification Methodology Development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows, and work hands-on with AMS IP Teams for AMS Behavioral Modeling flow and process experiments, demonstrations, adaptions, and deployment. The candidate will work with AMS IP teams including digital design, analog design, analog behavioral modeling and design verification members, apply and advance existing and evolving AMS Behavioral Modeling methodologies and processes, and contribute to establish and maintain Modeling Platform to ensure High Quality and High Efficiency of Pre-Si AMS Modeling, Validation and Verification delivery towards high quality silicon products. • Work in methodology development group to establish, streamline and enhance new and existing AMS Behavioral Modeling related development method, coding and validation process and integration flows. • Work with teams to enable deployment of new AMS Behavioral Modeling flow and processes through experiments, demonstrations, adaptions (for real projects in specified areas such as RF, etc) and integration. • Document on new flows and processes for AMS Behavioral Modeling. • Apply wide range of AMS Behavioral Modeling skills to help and support AMS IP or Chip Teams to establish or enhance new or existing Modeling capabilities, including but not limited to Model Development, Model Validation to ensure Consistency of Behavior with Original Circuit, Integration of Models into various Verification Environment, fixing Modeling issues found in simulation, etc. • Contribute to continuous improving on AMS Behavioral Modeling process for better quality and efficiency through methodology and process improvements. • Communicate and collaborate with global architecture, design, verification teams to address new needs or requirement on AMS Behavioral Modeling. Job Locations: • Taiwan:Hsinchu/Taipei • India: Bangalore • Singapore • USA:Santa Clara, CA/San Diego, CA 職缺需求 • Strong critical thinking and creative problem-solving skills. • Proficient on Verilog and SystemVerilog, able to develop synthesizable and behavioral code • Deep knowledge on digital design fundamentals, including Finite State Machine, etc. • Able to read schematics of Analog or Custom Design • Able to run and debug HDL and SPICE simulations • Good Understanding of simple Analog Mixed-Signal design elements such as op-amps, etc. • Hands on experiences with EDA tools such as Cadence Virtuoso DE • Previous experience on analog behavioral modeling is a huge advantage. • Ability to develop SystemVerilog Assertion is a strong plus • Experience on Digital and/or AMS Functional Verification is a strong plus • Knowledge of systems such as SERDES, PLL and/or WiFi, etc., is a strong plus • Ability to develop Verilog-A or Verilog-AMS models is a strong plus • Ability to develop Model Validation Environment is a strong plus • Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus.
1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution 職缺需求 1. MS +2yrs in EE/CS 2. SYN/APR/Signoff hands-on and tapeout experience in deep submicron technology 3. Tcl/Perl/script/C/C++ programming skills 4. Strong communication skills
電源管理晶片架構與系統設計(手機/車用) 低功耗設計技術開發 混合訊號數位 IP 設計: voltage regulator, ADC, system clocking and start-up, TOP infra/bus, peripheral designs 電源管理晶片整合: front-end and back-end integration 職缺需求 1. 年資: 3年 2. 熟悉 Verilog HDL, 數位設計流程與相關 CAD tools 3. 具數位/類比規格制訂與設計經驗 (nice to have) 4. 具晶片下線經驗與產品量產經驗 (nice to have)
1. 平台電源管理系統架構設計與規格定義, 包含功耗/溫度/性能等系統分析. 2. 系統應用詳細電源需求與控制架構之分析與優化 3. 電源管理芯片規格制定與新技術之開發. 職缺需求 1. 熟悉電力電子學相關領域, 包含電源管理芯片控制架構, 切換式電源轉換器, 線性穩壓器...等 2. 熟悉SIMPLIS/MATLAB...等模擬工具操作與建模 3. 良好地專案管理與溝通能力 4. 高速運算平台相關產品設計經驗 5. 熟悉功能安全與車用平台相關產品設計經驗
1. IEEE 802.3 Ethernet PHY & transceiver architecture & algorithm design 2. Digital signal processing of mixed-signal design 3. System simulation/model design for pre-silicon verification 4. System & algorithm design/simulation of high-speed I/F SerDes 5. Make contribution in standard organizations 職缺需求 1. MS or PhD degree in EE or Communication 2. Familiar with digital signal processing algorithm and practical implementation skill. 3. Familiar with the following programming languages : C/C++, Matlab 4. Familiar with communication theory. 5. Familiar with commercial wired or wireless communication specifications 6. It is nice to have algorithm development experience about one of the following systems: a. Ethernet 1G-T/2.5G-T/10G-T b. Ethernet 56G/112G/224G c. Digital-assisted mixed-signal design d. BT/LTE/WiFi/GPS/TV demod
1. 新產品開發討論 2. 電源管理IC及電源管理單元晶片整合 3. 與設計/生產/品保/軟體部門溝通協調 4. 晶片開發滿足智慧手機, IOT, 車用, 以及ASIC的需求 職缺需求 1. 熟悉晶片開發驗證量產流程 2. 熟悉類比電路設計及相關工具 3. 善於溝通協調及專案管理 4. 熟悉電源管理電路設計尤佳
1. Develop systematic algorithms to alleviate design challenges, including implementation, process what-if assessment, system performance evaluation, in advanced nodes or package 2. Closely work with foundry and EDA vendors to define innovative HPC, Chiplet design methodologies 3. Explore new EDA features and define improvement direction from MTK product requirements 職缺需求 Min requirement: 1. 4+ year work experiences in related fields with EDA tools 2. Fluent programming skill at least in one major language 3. Methodology development and deployment experience Preferred requirement: 1. With tapeout experiences 2. PPA boost, data analysis and algorithm design capability 3. Knowledge to perform DTCO and compare knob pros & cons 4. Strong paper publication records
1.Smartphone SLT軟體整合(C/Android) 2.Smartphone SLT量產測試自動化流程改善 職缺需求 1.精通C/C++ 2.熟悉 Android 3.溝通能力佳，需能跨團隊合作討論 4.具備Python能力尤佳 5.曾有過大型專案處理經驗尤佳
1. 數位晶片設計流程與整合 2. 熟悉低功耗的設計流程(和架構) 職缺需求 1. 具有 SoC 整合經驗 2. 熟悉低功耗設計並具備架構師的能力 3. 熟悉 IC 功耗計算 4. 具有 power integrity 相關的經驗
1. 開發用於模擬手機/平板/車用SOC功率消耗的平台 2. 協助IP, SOC與軟體團隊，維護用於功耗分析的資料庫，開發相關工具以輔助跨團隊的資訊整合 3. 優化系統效能，輔佐系統功耗相關決策的進行 職缺需求 基本需求 1. 資訊工程相關科系大學畢業，或擁有同等學歷與實務經驗 2. 五年以上C/C++軟體開發經驗 3. 熟悉資料結構與演算法 加分條件 1. 資訊工程相關科系碩士或以上學歷 2. 具有開發Python、Go或scripting language程式的經驗 3. 具備軟體工程相關操作的經驗，如版本控管、發布管理、測試自動化與程式品質控管 4. 具有開發資料庫相關應用的經驗 5. 具有開發後端或全端應用程式的經驗 6. 具備程式除錯、優化與自動化的能力 7. 具有SOC Power 架構設計或建模的經驗
1. Work on 7nm~3nm design implementation, methodology, and sign-off 2. Perform synthesis, DFT, floorplan, clock planning, place and route, timing closure, ECO, IR signoff, and physical verification 3. Manage schedule, resolve design and flow issues, drive methodologies and execution 職缺需求 1. MS +2yrs in EE/CS 2. SYN/APR/Signoff hands-on and tapeout experience in deep submicron technology 3. Tcl/Perl/script/C/C++ programming skills 4. Strong communication skills
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