影像處理（顯示）軟體工程師負責在 Linux/Android 平台上開發和整合影像處理軟體模組、流程及功能。主要職責包括： 1. 與顯示相關的影像處理控制，包括基本的視訊和圖像處理、畫質調校等 2. 開發裝置驅動程式、流程控制、演算法、軟題 service 等 3. 設計與審查display/graphic系統架構 4. Display/Graphic硬體驗證 5. 客戶支援及客戶功能開發 6. 作業系統 display/graphic HAL 層（如 Android HWC） 7. Linux 顯示子系統框架，例如 Direct Rendering Manager（DRM）、KMS、Framebuffer 8. 顯示介面：HDMI、DSI、DP、eDP 等 職缺需求 1.具有嵌入式Android and Linux 軟體開發者優先。 2.具有Linux內核的知識、設備驅動程式開發經驗及其 debug 工具和技能。 3.精通C/C++語言的編程和 debug 技能。 4.具有多處理器編程經驗。 5.具有影像處理開發經驗者優先。 6.具有軟體架構設計經驗者優先。
車用無線通訊軟體開發，包含： 1. 802.11 無線網路驅動程式與韌體開發 2. Android/Linux 嵌入式系統驅動軟件開發整合 3. WLAN/Wi-Fi通訊系統協定軟件設計及開發 4. 內部跨單位與車用平台單位及世界級車廠合作開發至產品量產 職缺需求 1. 碩士以上之通訊/電信/資訊相關科系畢業者佳 2. 熟悉作業系統、計算機結構與C語言 3. 熟悉 Android or Linux device driver & kernel 4. 熟悉802.11 protocol 並具備相關經驗
1. 設計、開發和維護安全啟動（Secure Boot）系統和引導加載程序（Bootloader）。 2. 實施和優化安全措施，包括密鑰管理、數字簽名和加密技術。 3. 與硬體工程師緊密合作，以確保驅動程式與硬體設計的兼容性。 4. 整合應用端的技術要求，與應用開發團隊合作，確保 secure IP 驅動程式的順利整合。 5. 進行安全漏洞分析，並提出相應的緩解策略。 職缺需求 1. 熟悉 Linux kernel OS 2. 熟悉 C, Makefile, GIT 3. 熟悉 driver 開發和維護 4. 好的溝通和團隊合作技能 5. 好的規劃執行能力 6. 了解 UEFI、Secure Boot 和 TPM 技術。 7. 具備密碼學知識，了解常見的加密算法和協議。
開發加速度計誤差估計和姿態估計的演算法。你會和衛星定位團隊一起合作，包括觀測量團隊、定位算法團隊，以及衛星定位及慣性導航融合算法團隊。這個職缺的主要工作是演算法開發，主要負責智慧型手機不同感測器與衛星定位融合的演算法開發。需對於從演算法開發到最終產品量產的完整流程充滿熱忱。 1. 探索並分析定位精度問題，以改善衛星定位晶片的定位性能 2. 開發數學模型和模擬軟體，做概念驗證 3. 參與路測並收集智慧型手機上的衛星定位晶片與慣性感測器的原始數據 4. 將算法實作成軟體程式，使其可以在晶片上即時運作 5. 測試軟體執行結果，除錯，改善並重複以上步驟來最佳化你的算法，並滿足客戶的需求 職缺需求 1. 熟悉卡曼濾波器的原理和實務開發，並且專精於感測器融合算法 2. 熟練於使用 C/C++, Python 做軟體開發 3. 對於解決實際路測問題和最佳化使用者體驗的工作有熱忱 4. 最佳化演算法的碩士或博士尤佳 5. 熟悉使用AI最佳化演算法來解決多變數的系統問題
高速類比 SerDes/PLL 電路設計 Work Location : 新竹/竹北/台北/台南 職缺需求 熟悉高速類比 SerDes 電路設計, 例如: CTLE, CDR, DFE, PLL, 以及 TX Driver 等
* Define and optimize SOC hardware architecture and associated software flows in aspects of system performance/power/area to improve MediaTek's product competitiveness. * Develop simulation and analysis platforms for performance/power/area analysis. 職缺需求 Job Requirements: 1. Practical experience in digital design or modeling (such as IP design/modeling, SoC integration/modeling) 2. Familiar with SoC architecture (could be any specific fields, such as Smartphone, DTV, display driver IC…) 3. Practical experience in system performance analysis, power consumption analysis, cost analysis, etc. Work experience in any of following fields would be preferred: 1. Bus interconnect (AXI/AHB/APB/ACE/CHI) 2. Network-on-Chip (NoC) 3. DDR memory system 4. Processors (CPU/GPU/AI accelerator) design 5. Cache coherence models (MESI/MOESI) 6. Analysis/estimation of SoC performance and power consumption
由於先進製程與高整合度晶片需要較長的研發時間及高製造成本，DV (Design Verification) 已成為聯發科技晶片開發流程中不可或缺的一環。 CDG DV部門負責開發與執行最高整合度 Smartphone，TV與ASIC驗證工程。 內容包含:整合型驗證環境開發，大數據分析與效能改善，BUS Fabric / EMI (External memory interface ) / Low power functions 驗證規劃及執行。 工作中需要設計及精進Verification plan/methodology/bench，對SOC系統有整體而深入的了解。 利用最新EDA tool and concept來完成你的驗證計畫。 工作地點:新竹/台北 職缺需求 1. Have a good command of Verilog / System Verilog / C++ / Perl 2. Have good senses of UVM and Formal verification method. 3. ARM Based SOC verification experience is a plus. 4. Chip Level verification experience is a plus. 5. Well Organized, methodical, and detail oriented. 6. Must be a team player and easy to work with
• Chip to Chip 介面類比 PHY 電路，例如 UCIe 標準或客製化的 Die to Die 連結類比電路設計 • HBM/DDR/LPDDR類比PHY電路設計與混合模式/高速電路設計等。 職缺需求 1. 碩士以上電子相關科系 2.熟悉UCIe/C2C/D2D/HBM/DDR/LPDDR/Serdes類比PHY電路設計。 3. 至少兩年相關工作經驗 4. 優秀的工作態度和良好的人際溝通能力。
1. 系統應用電源需求與控制架構分析 2. 電源管理晶片規格制定與驗證 3. 類比電路開發與驗證 4. 驗證電路板設計 5. 自動化測試開發 職缺需求 1. 熟悉電力電子相關領域包括控制架構, 切換式電源/線性電源轉換器...等 2. 熟悉印刷電路板相關工具與設技原理 3. 兩年以上電源管理相關工作經驗 4. 熟悉Labview或其他自動化測試編輯程式尤佳. 5. 優良的溝通能力與專案管理技巧.
開發手機/平板SoC模擬及分析平台， 從系統效能，功率消耗，溫度控制...等多重面向分析產品競爭力， 進而從系統角度優化硬體架構及軟體控制策略。 職缺需求 1. 熟悉以下其中一項: CPU/GPU/Memory架構、Android/Linux核心、系統效能分析、功耗估算、溫度模擬 2. 了解SoC架構，例如smartphone or DTV 3. 熟悉C++或Python程式設計 熟悉以下領域或經驗尤佳: * 熟悉SoC硬體設計流程
Multi-RAT (6G/5G/4G/3G/2G) modem development. This is a common job description. You may involve at least one or more topics in the following: (1) architecture planning 1.1 Modem/SoC TOP system architecture 1.2 Modem/SoC CPU system design 1.3 Modem/SoC DSP system design 1.4 Modem/SoC BUS system design (2) digital circuit design and verification 2.1 baseband modules 2.2 digital front-end modules 2.3 RF/mixed-mode digital control modules 2.4 Computer/network system modules 2.5 High speed interface design (3) IP integration 3.1 Clock/reset, test modeand low power mode design 3.2 floorplan and synthesis development (4) Design methodology 4.1 design flow enhancement (low power/verification/etc) 4.2 chip MP quality control flow 職缺需求 [Mandatory] 1. MS degree or above 2. Digital design work experience [Optional] Nice to have following items: 1. Knowledge of cellular modem and/or WiFi communication system 2. Digital baseband and/or digital frpnt-end design experience 3. Computer/Network architecture design experience 4. Digital design flow (RTL, front-end or back-end implementation and related EDA tools) experience 5. Platform, MCU and DSP understanding 6. RF/analog and/or 3rd party interface design experience 7. High speed interface design experience 8. Mixed signal design experience. 9. Timing and/or power sign off flow knowledge 10. Design verification (DV) knowledge 11. MP testing experience (CP/FT/SLT/etc)
MTK電源管理部門設計設計電源管理IC及電源管理單元以滿足各式各樣智慧手機, IOT, 車用, 以及ASIC的需求. 職缺包含: 1. DC-DC 轉換器 2. 線性電壓調節器 3. 切換電壓調節器 職缺需求 1. 熟悉Cadence IC設計軟體 2. 熟悉實驗室設備使用, ex: 示波器, 電壓電流量測儀, 電子負載 3. Switching regulator設計經驗 4. LDO設計經驗 5. 元件物理, 元件可靠度分析
1. 系統分析: 評估及分析系統效能/功耗及應用程式行為分析拆解 2. 工具開發: 開發特有的工具加速系統分析及性能決策(自動化/抽取性能指標) 3. 效能優化: 跨團隊合作優化系統效能/功耗或改善應用行為 職缺需求 1. 碩士以上 2. 1~5年相關產業經驗 3. 需要熟悉至少一項以上程式語言 (C/C++, Python, Bash, ...) 4. 有 Android/Linux 分析工具使用經驗為佳 (eg. systrace,perfetto,eBPF,...) 5. 有 功耗分析/功耗資料取樣工具使用經驗為佳 (eg. power monitor, NI DAQ, ...) 6. 熟悉ARM架構為佳 7. 具備軟體/系統行為/功耗分析相關經驗為佳 8. 具備工具開發經驗為佳
1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling 職缺需求 1. Familiar with digital IC design, implementation (DFT/STA/CDC), and FPGA emulation flow 2. Experienced in SoC architecture, embedded processor, and bus (AMBA AXI/CHI, NoC) system architecture design is a plus 3. Experience with memory subsystem design (cache, DRAM controller) is a plus 4. Experience with low power design (power manager) or analysis (power modeling, profiling) is a plus 5. Experience with functional safety design & flow (FMEA, FMEDA, DFA) is a plus 6. Experience with security hardware design is a plus
1. 從系統應用功秏分析, 與 IP, SoC 與軟體團隊合作, 推進 SoC low power 軟硬體架構的演進. 2. 產品規格定義時, 分析不同架構與 IP 選項, 在系統應用功秏體驗的差異, 產出產品應用 power dash board, 提供產品規格決策的依據. 3. 執行或協助功秏量測, 與power model預估的功秏做校正 4. 分析PMIC/Power rail 設計, SoC power state 與 data-path power等, 並且提出SOC 設計優化方案 5. 提出系統優化的方向, 達到最佳的產品電池使用續航時間與使用體驗 職缺需求 1. 五年以上IC 設計經驗 2. 熟悉SoC low power architecture/micro-architecture, 包括 clocking, multi-domain, power-state, DVFS, AVS 3. IP/SoC power optimization and estimation experience, including design and implementation 4. 有經驗/能力了解軟體實現/控制硬件power management 功能 熟悉以下領域與經驗尤佳 1. SOC or system power modeling 2. Android/Windows/iOS system 性能或功秏分析 3. Android/Windows/iOS system power management 開發 4. CPU/Memory/Interconnect architecture 5. Programming skill: Python, C/C++, PERL
1. Interpret customers’ functional safety requirements into SoC requirements 2. Define the SoC level architectures to meet functional safety requirements 3. Communicate and coordinate safety designs with cross-function IP teams 4. Perform system safety analysis (ex: FMEDA) #LI-JK1 職缺需求 1. MS+ in electronic engineering or computer science 2. Experience in IC design more than 7 years 3. Experience in SoC HW or SW architecture 4. Able to collaboratively work with cross-function organizations
1. Interpret customers’ functional safety requirements 2. Derive functional and technical safety concepts from functional safety requirements 3. Develop and review the safety IP design 4. Communicate and coordinate safety designs with IP teams 5. Perform system safety analysis (ex: FMEDA) 職缺需求 1. MS+ in electronic engineering or computer science 2. Experience in IC design 3. Able to collaboratively work with cross-organizations 4. Familiar with automotive functional safety (ISO-26262) (preferred) 5. Familiar with automotive system architectures (preferred)
解讀客戶的網絡安全需求 從網絡安全需求中推導出功能和安全概念 制定和審查安全系統架構 與 IP 團隊和客戶溝通和協調安全設計 執行系統安全分析（例如：TARA） 職缺需求 電子工程或計算機科學碩士+ 10年以上IC設計或IC固件經驗 熟悉SoC安全架構 熟悉汽車行業（優先） 熟悉汽車網絡安全（ISO-21434）（優先） 熟悉汽車系統架構（優先）
1. Define power states and management hardware architecture for optimal power performance. 2. Design microprocessor-based power management controller and HW assistance designs. 3. Define power architecture by performing power rail tradeoff analysis with adaptive voltage scaling consideration 職缺需求 1. Define power management mechanisms based on product requirements, combining both software and hardware considerations. Familiarity with power domain architecture and planning is important. 2. A strong understanding of computer architecture and experience in low power design and power optimization techniques is required. 3. Experience with common SOC components such as embedded processors (DSP/MCU) and bus (ARM bus) system architecture design is advantageous. 4. Proficiency in power modeling and power analysis is a plus. 5. Capable of performing power performance analysis, considering trade-offs with PCB area and costs is a plus. 6. Knowledge of Primetime STA analysis and timing analysis methodologies. 7. Proficient in RTL coding and scripting languages like Python or Perl. Experience with UPF and CLP is a bonus. 8. Strong problem-solving and analytical skills.
1. Develop and implement tailored DRAM controller/PHY solutions for automotive applications. Validate functionality, improve design revisions and meet performance targets as well as system requirements. 2. Perform rigorous design testing and debugging in automotive environments. Troubleshoot and propose solutions for any issues occurring in post-silicon validation. 3. System Level Cache Design & Implementation: Design and implement system level cache strategies to optimize performance and efficiency across our product range. 4. System-Level Understanding: Exhibit a system-level understanding of performance trade-offs, system architecture, memory subsystems, and various memory technologies (DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc.). 5 . Ensure that all designs comply with automotive industry standards and regulations, such as ISO 26262 and Automotive SPICE. 職缺需求 1. Proven industry experience in the design and implementation of memory controllers/PHY. 2. Solid understanding of memory hierarchies, cache design and management. 3. Knowledge of system design and modeling tools. 4. Experience in designing and optimizing system level cache for automotive applications. 5. Previous experience with automotive-grade DRAM interface standards and memory technologies such as DDR3, DDR4, DDR5, LPDDR3, LPDDR4, LPDDR5 etc. 6. Familiarity with automotive safety standards such as ISO 26262.
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