職位與職責： 1. 定義 GPU 編譯器軟體架構及介面。 2. 開發/實作 GPU 編譯器流水線、連結以及各種最佳化/轉換。 3. 與驅動程式團隊及硬體團隊合作，實作新的 API 與硬體功能。 4. 與驅動程式團隊及硬體團隊合作，改善/調整效能與功耗。 5. 執行並交付專案，以達成里程碑與進度要求。 6. 分析並除錯程式碼生成相關問題。 7. 分析並影響未來 GPU 架構的設計。 8. 與內部及外部團隊建立可靠且值得信賴的合作關係。 職缺需求 應徵要求: 1. 具備電腦科學、電機、電腦工程或相關領域之學士、碩士或博士學位（或同等學歷）。 2. 擁有產品編譯器、編譯器工具（如組譯器、連結器）開發相關工作經驗。 3. 具備 C/C++ 程式設計之實作知識與經驗。 4. 具備業界領先編譯器最佳化/轉換技術之實作知識與經驗。 5. 具備 LLVM 之實作知識與經驗。 6. 具備優秀的書面與口語溝通能力。 7. 具備良好的團隊合作能力與執行力。 8. 具備強大的問題解決、根本原因分析及除錯能力。 9. 具備高度的自我驅動力。 加分條件： 1. 具備 GPU/GPU 流水線及 GPU 架構相關知識與經驗。 2. 具備 SIMD 架構相關知識與經驗。 3. 具備 D3D、Vulkan/OpenGL、OpenCL API 相關知識與經驗。 4. 具備於編譯器、工具或最佳化開發中導入 AI 技術之相關知識與經驗。
Role and Responsibilities • Responsible for GPU cluster uArch specification, PPA (power, performance and area) optimization for industry-leading GPU hardware IP • Collaborate with Arch/Model/SW team, develop cluster level HW specification that meets feature functionality and PPA metrics • Collaborate with Arch/SW/Design team to identify and solve performance bottlenecks, power/area inefficiency issues • Guide IP design process all the way from RTL coding, verification to tape out and post-silicon debug • Proficiently use AI agent and tools to improve RTL coding, function debug and PPA analysis productivity • Execute & deliver to meet milestones/schedules. • Analyze and debug code pre-silicon and post-silicon issues. • Analyze and influence future GPU architectures. • Construct reliable & trustable relationships across teams internally & externally. • Delivering best in class GPU IP for mobile, automotive, laptop and ASIC applications 職缺需求 Requirement • MS or PhD degree or equivalent in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 6+ years of working experience on RTL design, micro-architecture, and architecture for GPU/Graphics domains OR 8+ years of working experience on RTL design, micro-architecture, and architecture for Multimedia (video, camera, image processing, etc.), neural network accelerators, matrix computation, CPUs, or cache systems. OR 10+ years of working experience on RTL design, micro-architecture, architecture, and modeling for a variety of digital circuits. • Hands-on experience on SystemVerilog/VHDL/C/C++ and scripting programming. • Hands-on knowledge/experience on SoC architecture, performance tuning, area/power optimization flow. • Excellent interpersonal skills including both verbal and written communication • Strong leadership, self-driven, team player • Strong problem solving, root causing and debugging skills. • Fluent English communication skills (both spoken and written) to collaborate effectively with international teams. • Able to work in a dynamic and fast changing environment • Preferred skills: -Knowledge/experience on GPU pipeline (Shader, Texture, Geometry, Pixel, Raytracing, Memory etc.) and GPU architecture. -Knowledge/experience on computer architecture, parallel computing or cache system. -Knowledge/experience on D3D, Vulkan/OpenGL, OpenCL APIs. -Knowledge/experience on floating point data processing. -Proven track record in performance tuning and area/power optimization -Experience collaborating with worldwide, cross-functional engineering teams.
Role and Responsibilities • Collaborate with architects and design leads to define and document micro architecture of sub-modules of shader subsystem • RTL coding and deliver high quality scalable design to meet PPA requirements • Collaborate with verification team for feature description, testplan, and coverage closure • Assist DV engineers for debugging functional, performance, power test failures • Collaborate with synthesis and PD team for timing and area closure • Collaborate with power team to identify power saving opportunities and meet power target • Assist block team manager in strategy, planning, scope estimation, and progress reporting 職缺需求 Requirement • MS or PhD degree or equivalent in Electrical Engineering, Computer Engineering, Computer Science, or a related field. • 5+ years of working experience on RTL design and overall ASIC design flow • Working experience of designing high throughput and low latency designs • Good knowledge of synthesis and PD flows • Good knowledge of different design techniques and their implications on physical design • Hands-on experience on SystemVerilog/VHDL/C/C++ and scripting programming • Hands-on knowledge/experience on pipeline design, digital signal processing, area/power optimization flow • Good teamwork and excellent interpersonal skills including both verbal and written communication • Strong problem solving, root causing and debugging skills • Good English reading and writing capabilities for technical documentation. • Able to work in a dynamic and fast changing environment • Preferred skills: -Knowledge/experience on GPU pipeline (Shader, Texture, Geometry, Pixel, Raytracing, Me
軟體專案經理涵蓋以下工作職責 - 與產品經理（PM）/業務團隊合作，開發新垂直領域與新專案的概念驗證（PoC） - 負責客戶與內部的專案管理，包括專案規劃與排程、團隊資源管理、專案風險與問題管理 交付成果 - 成功完成 Design‑In，使產品能夠被客戶設計採納。 - 確保專案管理透明且高效，如期完成關鍵里程碑。 - 推動專案進入量產階段，協助客戶產品按時上市，實現營收。 職缺需求 - 碩士學位，主修電機/電子工程、資訊工程、軟體工程或相關管理領域 - 具備 MBA、行銷或專案管理碩士學位，受過軟體工程專業培訓及工作經驗者 專業經驗 - 至少6年以上工作經驗，包含至少4年實務專案管理經驗，具 Design‑In（客戶產品採用） 與 概念驗證（PoC） 專案經驗者尤佳 - 有與 軟體設計團隊、業務/PM 團隊以及品牌／OEM／ODM 客戶合作，將產品從 PoC 推至量產的成功經驗 - 曾在全球或多據點環境下協調 跨功能團隊（研發、製造、品質、第三方廠商等）完成專案的經驗 專案管理能力 - 具備風險控管，分類、評估及緩解能力 - 熟練使用 Microsoft Project、Excel、JIRA 等基礎工具。熟悉 AI 工具尤佳 - 製作專案報告、定義 KPI 指標供內部團隊與客戶隨時掌握專案進度與風險 溝通與協調 - 英文與中文（讀寫與口說）流利 - 主持內部團隊與外部客戶的會議，workshop與design review，維持雙方的有效溝通及互動 - 具說服力及談判技巧，能快速化解內外部的歧異並在不同功能領域間取得共識 技術背景 - 具軟體專業且一定程度了解半導體/SoC開發相關流程 - 熟悉客戶產品開發流程如PoC → Design‑In → 品保（QA） → 量產（MP） 領導與團隊管理 - 有規劃與分配團隊資源（人員、設備、外部廠商）的實務經驗。 - 能指導與培育團隊成員的專案管理能力 - 在期限緊迫、壓力大的情況下，能保持冷靜並作出有利公司及客戶的決策
About the Role: Bring your GPU driver expertise and work closely with our Architecture and Micro-architecture teams. In this role, you will contribute across the GPU software stack and help extract maximum performance from the silicon while supporting the development of our next-generation GPU designs. This is not a siloed driver role. You will have opportunities to work across industry-standard graphics and compute APIs, kernel-mode drivers, GPU firmware, performance optimization, and hardware/software integration. What You’ll Do — The Full Stack: • API Layer: Develop, debug, and optimize features for industry-standard APIs including Vulkan, DirectX, OpenGL ES, and OpenCL. • Kernel & Firmware: Work on kernel-mode drivers and GPU firmware to improve hardware control, stability, scheduling, memory management, and execution efficiency. • Performance: Analyze and optimize bottlenecks across the stack, including driver overhead, memory bandwidth, GPU scheduling, compute throughput, and power/performance tradeoffs. • Cross-Team Collaboration: Work closely with Architecture, Micro-architecture, Compiler, and GPU Model teams to validate GPU behavior, debug complex issues, and improve software/hardware interaction. • System-Level Debugging: Investigate issues across user-mode drivers, kernel-mode drivers, firmware, and hardware models to improve stability, correctness, and performance. Who You Are: • You have 5+ years of experience in GPU drivers, graphics systems, embedded software, or low-level systems software. • You are strong in C/C++ and comfortable working close to hardware. • You have experience with one or more industry-standard APIs such as Vulkan, DirectX 12, OpenCL, or OpenGL ES. • You understand GPU or SoC internals, including areas such as memory hierarchy, command submission, scheduling, synchronization, pipeline architecture, or performance bottlenecks. • You enjoy working across technical boundaries and are excited by the opportunity to contribute from API-level software down to kernel drivers, firmware, and hardware-facing components. Why This Role? • No Silos: You are not restricted to only one layer of the stack. You will have the opportunity to work across APIs, drivers, firmware, and performance. • Hardware-Software Impact: Your work will help the software stack fully utilize GPU hardware capabilities. • Next-Gen GPU Exposure: You will collaborate with architecture, compiler, and modeling teams on technologies that shape future GPU products. Ready to work across the entire GPU stack? Apply today. 職缺需求 Who You Are: • You have 2+ years of experience in GPU drivers, graphics systems, embedded software, or low-level systems software. • You are strong in C/C++ and comfortable working close to hardware. • You have experience with one or more industry-standard APIs such as Vulkan, DirectX 12, OpenCL, or OpenGL ES. • You understand GPU or SoC internals, including areas such as memory hierarchy, command submission, scheduling, synchronization, pipeline architecture, or performance bottlenecks. • You enjoy working across technical boundaries and are excited by the opportunity to contribute from API-level software down to kernel drivers, firmware, and hardware-facing components.
Responsible for GPU HW development environment tool/flow maintenance and database (perforce) management. Effectively support DE/DV smooth development. 職缺需求 Minimum two years experience, MS/BS degree in EE/CS major. Familiar with digital ASIC design tools like Synopsis DC, VCS, Verdi, UVM, Spyglass/Leda, Cadence LEC, JasperGold, VC formal, Ansys PowerArtist. Profiling in perl/tcl/python scripting, capable of leveraging AI tools to write scripts code
1. 負責SOC內 bus 數位系統的 SystemC 平台建模與模擬，包括功能建模與性能分析。 2. 根據系統規格，建立可重複使用且具延展性的 SystemC 模型，支援系統架構規劃與驗證。 3. 參與 SoC（System-on-Chip）/IP 之行為層及高層次抽象（TLM, Transaction-Level Modeling）模型設計與驗證。 4. 與硬體、軟體和驗證團隊協同合作，協助流程整合、聯調與問題分析。 5. 撰寫技術文件與模型說明，支援團隊設計、驗證及客戶應用。 職缺需求 1. 熟悉 SystemC/C++ 程式設計與物件導向概念。 2. 具備晶片或系統平台高層次建模經驗尤佳。 3. 具備 SoC 架構與匯流排協定（如 AXI, AHB, CHI 等）基礎知識尤佳。 4. 熟悉 Linux/Unix 開發環境。 5. 良好的跨團隊溝通能力及問題解決能力。 加分條件： 1. 具備 TLM-2.0、硬體軟體協同模擬、或虛擬平台開發經驗。 2. 熟悉 Verilog 或其他硬體描述語言。 3. 有 Python/Perl/Shell script 自動化經驗尤佳。 4. 有與國際團隊協作經驗。
We seek a skilled and visionary AI Computing Platform Software Planner to drive innovation and development across our AI platform products. This role requires close collaboration with leading technology partners – Google (Android OS), Microsoft (Windows) - to define, plan, and execute software features that enable advanced AI capabilities in our computing platforms. 1.Software Feature Set Planning & Decision Making 2.Execution Planning 3.Cross-Partner Collaboration 4.Platform Integration & Validation 5.Documentation & Communication 職缺需求 + Bachelor’s or Master’s degree in Computer Science, Software Engineering, or related field. + 5+ years experience in platform software planning or technical program management. Demonstrated expertise with Android, Windows, and Linux OS development ecosystems. + Strong knowledge of modern AI and ML technologies (TensorFlow, PyTorch, ONNX, NNAPI, DirectML, etc.). + Excellent communication, negotiation, and documentation skills. + fluent English speak
1. Familiar with DFT plan, methodology, implementation 2. Familiar with new DFT flow such as SSN, HSIO 3. Familar with STA, timing analysis 職缺需求 1. Familiar with digital IC design flow 2. Experienced in STA and Tessent or TetraMax flow
1. SOC platform 架構與RTL implementation 2. 負責 IP/子模組之 RTL 整合，組成 SoC (System-on-Chip) 或子系統的頂層設計。 3. 依據設計規格，串接不同來源或平台的 RTL，確保各模組間介面相容與功能正確。 4. 撰寫與維護整合 RTL 的頂層模組、配置腳本及連結測試環境。 5. 針對整合後的設計進行功能模擬、靜態時序分析（STA）、Lint、CDC 及等驗證工作，並協助 debug。 6. 與軟硬體、驗證、後端設計等團隊密切合作，確保整合流程順利與產品交付時程。 7. 編寫設計文件及協助設計交付相關事務。 職缺需求 1. 熟悉 Verilog 等硬體描述語言。 2. 有 RTL 設計、整合或 SoC 頂層建構經驗優先。 3. 具備基本數位電路原理與 SoC 架構知識。 4. 熟悉 EDA 工具（如：模擬、綜合、Lint、STA）。 5. 良好的團隊合作能力與溝通技巧，積極主動的工作態度。 加分條件： 1. 有 IP/SoC 頂層集成經驗。 2. 熟悉腳本語言（如 Perl、Python、Tcl）。 3. 具備 CDC/RDC/Lint 分析經驗
1. SoC low power design, integration, and modeling 2. SoC adaptive voltage scaling development 職缺需求 1. Familiar with digital IC design, DFT, and FPGA emulation flow 2. Experienced in chip integration 3. Experience with low power design
1. 開發多模式 NR / 6G / NTN DSP 韌體： 包含狀態機（State Machine）、通道排程（Channel Scheduling）及數據機控制（Modem Control）韌體設計。 2. 在嵌入式系統中實作 OFDM 通訊訊號處理與理論。 3. 將數位通訊演算法移植或開發於專用指令集處理器（ASIP）或數位訊號處理器（DSP）架構之上。 職缺需求 1. 熟悉 C 語言與資料結構。 2. 熟悉數位通訊理論。 3. 熟悉嵌入式系統開發。 4. 具備 3GPP NR / NTN 規範研讀經驗或實體層（L1）開發經驗者尤佳。
1. 5G/6G通訊IP開發. 2. 多模(5G/6G)解調架構開發以及RTL coding/verification/integration 職缺需求 1. 具備無線通訊系統相關知識. 2. 熟悉數位IC設計流程.
We are seeking a knowledgeable and analytical AI Computing Platform Hardware Planner to drive competitive benchmarking across CPUs, GPUs, and NPUs. This role requires deep familiarity with performance metrics—such as perf/W, tokens/sec—and industry standards. You will collaborate closely with QA teams to produce comprehensive insights comparing MediaTek’s computing platforms with leading competitors, including Intel, Qualcomm, and Apple. Key Responsibilities: 1. Competitive Benchmarking 2. Industry Knowledge and Analysis 3. QA Collaboration & Insight Generation 4. Reporting & Communication 職缺需求 + Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. + Proven experience in hardware benchmarking and AI workload analysis. + Strong knowledge of CPU, GPU, and NPU performance metrics (perf/W, tokens/sec, throughput, latency). + Excellent teamwork and communication skills.
1. Work on AI development for design flow 2. Perform floorplan, clock planning, place and route, timing closure, ECO, IR signoff flow automation 職缺需求 1. MS in EE/CS 2. AI knowledge 3. Python/Tcl/Perl/script/C/C++ programming skills 4. Strong communication skills
負責PCIe軟體開發，硬體功能驗證，以及量產support. 1. FPGA/SoC 驗證 2. Linux/RTOS/Window PCIe driver 開發 3. 軟硬體問題分析與解決 4. 系統規格討論 5. 客戶問題支援 職缺需求 1. 熟悉 PCIe 標準規範 2. C/C++ 程式設計語言 3. 具嵌入式系統開發經驗 4. 具 Linux 環境程式開發經驗
1. Work with Sales teams to get design wins for MediaTek Connectivity (Wi-Fi, and BT) at Tier-1 and leading customers 2. Promote Product Roadmap and Technology 3. Develop Ecosystem: discuss with partners (chip, HW, SW) to align on product roadmap and Go-To-Market strategy 4. Drive customer design wins and help BU to manage customer programs 5. Understand Connectivity industry trends and drive competitive positioning 職缺需求 1. Experienced in Wi-Fi/BT and other connectivity technology and products 2. Knowledgeable in mobile end product requirements 3. Experience in frontline product marketing promotion 4. Have business savvy in dealing with customer, ecosystem companies and partners
1 . 熟悉數位IC整合流程, 包含RTL, 模擬, 時序分析, 功耗分析, 量產問題分析. 2 . 低功耗分析 3 . 系統架構分析經驗是加分項 4 . 熟悉DFT是加分項 職缺需求 1 . 熟悉數位IC設計是加分項 2 . 有ARM bus系統設計經驗是加分項 3 . 有系統驗證經驗是加分項
－Partner closely with software engineering leaders (VPs and Directors) to ensure rapid development progress, faster decisions through clear priorities, and expedient closure of blockers －Maintain a dashboard and regularly present progress reports to company and partner executives, highlighting key milestones, risks, and next steps. Provide clear context and recommendation on major decisions －Facilitate effective communication between engineering teams and partners regarding issues, needs, and requirements. －Assist engineering teams in prioritizing and triaging customer requests to align with business objectives and resource availability. －Manage escalations from partners, identifying root causes and driving resolution in coordination with relevant teams. －Monitor and evaluate execution costs, including tools, equipment, and headcount, and prepare recommendations to support management approval processes. －Build and sustain strong working relationships with partner software leaders, ensuring transparent communication, timely updates, and effective handling of partner requests. －Collaborate with product planning to lead engineering teams in developing demos and performance benchmarks 職缺需求 －Bachelor’s Degree or higher in Computer Science, Electrical Engineering, Information Systems, Business, or related field. －5+ years of experience in software product management or project management, preferably in semiconductor, chip, or embedded systems domains. －Experience working with cross-functional engineering teams and external partners/clients. －Strong organizational and project tracking skills; experience with creating and maintaining dashboards/reports. －Excellent English communication (verbal and written) and interpersonal skills, with ability to convey technical concepts to executives and non-technical staff. －Demonstrated ability to manage escalations and resolve conflicts in a structured, time-sensitive manner. －Proactive and collaborative mindset focused on building rapport and trust with partners and internal stakeholders. －Familiarity with semiconductor, chip software development process, and related tools/equipment is highly desirable.
開發以 LLVM 或 MLIR 為基礎的 NPU compiler 職缺需求 熟悉LLVM 或 MLIR compiler為必要。 熟悉以下任一項為加分：GCC, TVM, and RISC-V, Halide, C 語言編譯器架構或TFLite 編譯器架構
上刊登職缺 
