我們正在重新定義晶片設計的未來，不再僅僅是設計電路，而是打造一個能夠「自我演化」的晶片設計大腦。我們正在招募具備 IC 設計與 AI 技術熱忱的工程好手，一起開創 IC 設計新時代！您將與跨領域專家攜手打造 IC Design Autonomous 的未來——運用最先進的 GAI 技術，實現從規格生成、RTL 編碼到自動化 QC 錯誤清除的完整 IC 生命週期自動化，並建立自我進化的生產力循環，讓 AI 真正落地於 IC 設計流程！ *任務描述 - 全流程自動化：設計並實作端到端的自主設計代理人 (Agentic AI) 框架，涵蓋 Spec-to-RTL 與自動化 QC 修復 - 架構演進：利用 GAI 技術進行 PPA (Power, Performance, Area) 優化，開發具備自我回饋、自我學習能力的設計閉環 - 技術領導：指導跨團隊協作，將 IC 設計流程中的自動化瓶頸，轉化為 AI 可理解並自主執行的架構 - 知識體系建構：構建領域專屬的 Knowledge Base 與 Multi-Agent 協作框架 - 研究創新：研讀最新技術、發表專利論文，將前沿研究轉化為實際應用 職缺需求 1. IC 設計專業：具備數位IC設計經驗，熟悉 Spec 編寫、Architecture 設計、RTL 整合；精通 Verilog/SystemVerilog 2. AI技術融合：熟悉 AI (GAI/LLM/DL) 技術及其實務應用，包括 LLM 推論、Prompt Engineering、RAG 及 LLM Model Finetune 3. Agentic AI：熟悉 Agentic AI 平台及技術，包括 Agent Skills、MCP 及 CLI；具備 Agentic Workflows 設計能力 4. 程式開發：精通 Python 及 AI 框架；熟悉 C/C++、TCL 程式開發；具備 AI 應用於工程流程實績 5. 開拓者精神：挑戰不可能，從零到一建立系統的勇氣 6. 策略性思維：預見技術路徑，具備長期規劃能力 7. 跨領域溝通力：作為 IC 與 AI 領域間的橋樑，轉化複雜概念；中英文溝通能力佳，能團隊合作 8. 抗壓與韌性：在高度不確定性環境中穩定輸出，快速學習調整 9. 加分條件 - 具備 EDA 或 IC Design 流程/平台開發經驗 - 熟悉 EDA 工具與 AI 技術整合及自動化 - 6年以上數位 IC 設計經驗
1. Bus and Architecture design and RTL implementation of Smartphone chipset 2. ASIC and Smartphone SoC and mobile computing platform design. 3. System bus and mobile peripheral designs 4. SoC system performance analysis 職缺需求 1. Familiar with digital IC design, DFT, and FPGA emulation flow 2. Experienced in SoC architecture, Embedded Processor (DSP/MCU), and bus (ARM bus) system architecture design is a plus 3. Experienced in chip integration is a plus 4. Experience with External Memory Interface design is a plus 5. Experience with system verification job is a plus 6. Experience with security hardware design is a plus 7. Experience with DRAM bandwidth improvement is a plus 8. Experience with analog/digital interface design is a plus
We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful DFT architects interact with many external teams and must confidently represent his/her organization. Key Responsibilities • Drive DFT Excellence: Define DFT architecture specifications that enhance ATE and production test environments, optimize test costs, and improve quality across future MTK ASIC product portfolios. • End-to-End DFT Leadership: Manage comprehensive DFT activities spanning architecture definition, design implementation, verification, and test deployment for new product launches • Manufacturing Integration: Serve as a key contributor within MTK’s Global Quality and Operations organization to deliver optimal manufacturing test solutions from early product conception through post-silicon validation • Design Collaboration & Quality Assurance: Partner closely with design teams to ensure accurate implementation of DFT structures and compliance with specifications • Cross-Functional Team Coordination: Lead internal DFT teams in developing and implementing robust test solutions aligned with architectural requirements • Yield Optimization Strategy: Develop comprehensive plans for diagnosability enhancement and systematic yield improvement • Location: Hsinchu, Taipei, Singapore, USA 職缺需求 • Proven DFT Expertise: Extensive engineering experience across complete DFT lifecycle, including pre-silicon architecture definition through post-silicon validation and production ramp • Architecture Leadership: Demonstrated success in creating and implementing complex multi-die DFT architectures for advanced semiconductor products • Comprehensive DFT Implementation: Hands-on experience with Scan and Scan Compression techniques at both IP and SoC levels, with deep understanding of integration challenges • DFT Tool Proficiency: Strong command of industry-standard DFT tools and ATPG methodologies including Stuck-At, At-Speed, and Path-Delay fault models with scan compression techniques • Memory Test Expertise: In-depth knowledge of MBIST architecture, implementation, and optimization strategies • High-Speed Interface Knowledge: Experience in PHY design, high-speed IO protocols, digital communication interfaces, and functional test development • Advanced DFT Technologies: Knowledge of Tessent Streaming Scan Network (SSN); hands-on implementation experience highly preferred • Silicon Debug Proficiency: Practical experience with post-silicon debugging techniques and lab equipment including oscilloscopes, logic analyzers, and ATE platforms • Digital Design Foundation: Solid understanding of Verilog RTL, synthesis optimization, physical implementation flows, and Static Timing Analysis • Verification Methodology: Strong grasp of modern verification approaches and best practices • FPGA Design Experience (Preferred): Familiarity with FPGA logic design, synthesis workflows, and implementation methodologies • Collaborative Team Player: Excellent communication skills with proven ability to work effectively in cross-functional team environments and drive consensus across diverse stakeholder groups • Education: M.S. or Ph D. in Electrical Engineering, Computer Engineering, or related field.
1) 負責設計與定義先進4G, 5G 及 6G通訊系統內數據擷取控制系統架構, 以作到系統行為分析, 系統效能優化 及 問題解決。 2) 開發、優化並維護數據擷取控制系統的底層驅動程式與軟體控制流程。 3) 研究並導入以AI為基礎的自動化工具，以強化問題診斷、異常偵測與數據分析能力。 職缺需求 1) 熟悉 C, 具 C++/Python 尤佳。 2) 具有 Driver 或 Kernel (任何 RTOS) 或 embedded system 相關開發經驗尤佳，
* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. * (If manager) Manage the design architecture team, focusing on both technological advancement and talent development. 職缺需求 Core Requirements: * Proven experience in SoC system or subsystem architecture design with a track record of successful mass production (MP). * Strong team collaboration skills, including experience working in multi-site environments. * Experience in one or more of the following areas: 1. Camera sensor and image processing or computer vision architecture design 2. Heterogeneous computing architecture or efficient datapath design, covering CPU, NPU, and Camera Processing Elements (PE) 3. AI computing architecture 4. SoC chip platform architecture, such as memory fabric and power systems * (if manager) experienced in department or division manager. Bonus: Knowledge or experience in IVI/Cockpit and ADAS/AD application scenarios Knowledge or experience in designing Cockpit/ADAS AI models Additional proven experience in subsystem architecture design with mass production (MP)
At MediaTek, we are at the forefront of enabling device + cloud hybrid architectures for generative AI. On-device AI offers significant advantages, including low latency, enhanced security, privacy, and personalization through fine-tuning to meet specific user needs. As an AI SDK/IDE Software Engineer, you will be responsible for developing and enhancing our NeuroPilot SDK workflow. This role involves designing and implementing features that support neural network development stages, including network conversion, optimization tuning, profiling and accuracy analysis. You will work closely with cross-functional teams to ensure a seamless user experience and robust functionality. We are seeking talented individuals to join our team and contribute to this cutting-edge field. 職缺需求 Key Responsibilities: 1. Design and Development: Develop and enhance NeuroPilot SDK architecture for generative AI workflow. 2. Performance Optimization: Conduct performance analysis and implement optimizations for runtime efficiency and memory usage. Required Qualifications: 1. Proficiency in C/C++ programming 2. Proven experience in developing and optimizing software for AI applications. Preferred Qualifications: 1. Experience of development of AI compiler, such as MLIR, TVM, XLA or IREE 2. Experience with AI frameworks such as PyTorch or ONNX
高速類比SerDes電路全客製化佈局設計及自動化流程設計 職缺需求 * 學士或碩士 EE, CE, CS 等相關領域 * 至少 3 年以上相關3D-IC矽中介層或類比、射頻等電路佈局經驗 * 熟悉類比、射頻電路布局設計及驗證 * 熟悉電路布局EDA工具，如Virtuoso, Calibre, Laker, Custom Compiler, etc. * 具備先進FinFET製程的電路佈局經驗 * 具備程式能力設計自動化流程或APR經驗會是個加分項目 * 具備獨立作業及良好的團隊合作能力 * 英文溝通能力與全球團隊合作
* Lead specific architectural domains for SoC architecture design and product technical feasibility studies (e.g., AI, ISP, heterogeneous computing, memory, interconnect, power, safety, vehicle E/E, in-vehicle network). * Lead or support automotive SoC architecture, focusing on system performance and power based on product requirements. * Lead or support technical feasibility studies of product requirements; collaborate with domain architects and product marketing to develop competitive product design specification. 職缺需求 Core Requirements: * Proven experience in SoC system or subsystem architecture design with a track record of successful mass production (MP). * Strong team collaboration skills, including experience working in multi-site environments. * Experience in one or more of the following areas: 1. Camera sensor and image processing or computer vision architecture design 2. Heterogeneous computing architecture or efficient datapath design, covering CPU, NPU, and Camera Processing Elements (PE) 3. AI computing architecture 4. SoC chip platform architecture, such as memory fabric and power systems Bonus: Knowledge or experience in IVI/Cockpit and ADAS/AD application scenarios Knowledge or experience in designing Cockpit/ADAS AI models Additional proven experience in subsystem architecture design with mass production (MP)
1. 負責多媒體與周邊裝置的軟體及韌體開發（包含框架、驅動程式及功能開發）。 2. 執行客製化晶片功能驗證。 3. 進行系統效能優化及問題分析。 職缺需求 1. 熟悉 C/C++ 2. 有ARM Linux embedded system 開發經驗者佳 3. 有訊號處理經驗者佳 4. 樂於學習新技術
• 規劃從silicon bring up到量產全過程的測試程式（包含 CP/FT、系統測試、DVT、HQA、相關性分析及 DPPM 降低）。 • 開發功能測試/ATPG/MBIST測試碼，涵蓋程式開發、模擬、coverage收集、機台測試程式生成以及在測試機上的驗證。 • 基於對CPU design的了解以及實驗設計, debug post-silicon DPPM, RMA問題。 職缺需求 1. 精通 C 與組合語言（Assembly）編程、Verilog/SystemVerilog、ATPG 測試碼生成工具及 MBIST 測試碼生成工具。 2. 具備 ARM CPU 架構及 AMBA IP 相關知識。 3. 熟悉 DFT（可測性設計）、MBIST 及 SRAM。 4. 具備 Perl 或 Python 程式設計能力。
Objective: 1. Play a critical role in driving cross functional team in enabling critical manufacturing ramp and achieving aggressive time-to-market (TTM) goals 2. Identify ENG sample supply chain risk and mitigation plan, ENG sample delivery demand & commit, ENG to MP supply chain transition to PP Job Description: 1. Overseeing the integration of all ENG supply chain activities, including procurement, manufacturing, logistics, and quality 2. Leading cross-functional teams to identify and mitigate ENG supply chain risks 3. Developing and implementing strategies to optimize constrain ENG sample supply and flow 4. Ensuring on-time delivery of ENG samples, materials and components to support project verification and qualification 5. Collaborating with engineering and product development teams to ensure product manufacturability 6. Continuously monitoring and improving ENG supply chain performance metrics 7. Fluent transition for the ENG supply chain to MP supply chain with PP 職缺需求 1. Highly motivated, proven experience in supply chain integration and cross-functional collaboration 2. Strong analytical and problem-solving skills 3. Excellent communication and interpersonal skills 4. Experience managing and driving high-performing teams 5. In-depth understanding of supply chain and lean manufacturing principles 6. ≥3 years of experience in semiconductor, especially for advanced wafer fabrication or package
1）支持生產製造，負責綜合良率 2）管理OSAT，監督組裝和測試生產流程 3) 日常管理生產暫停批次處置 4）透過CIP推動生產良率和測試時間的提高 職缺需求 1. 積極主動，具備供應鏈管理與跨職能協作經驗 2. 較強的分析與解決問題的能力 3. 優秀的溝通與人際溝通能力 4. 擁有管理和領導高績效團隊的經驗 5. 深入了解供應鏈和精實製造原則 6. 3年以上半導體產業經驗，尤其擅長先進晶圓製造或封裝
1. IC封裝/晶圓凸塊技術開發與管理 2. 與封裝廠合作完成規劃之技術開發 3. 先進封裝技術開發,品質驗證與生產良率管理 4. 定期與不定期執行bumping/fan-out/WLCSP廠品質稽核 職缺需求 1. 碩士以上畢業並有 8 年以上IC封裝相關工作經驗 2. 熟悉IC封裝成本結構,生產技術,製程,設計,結構與材料,並有解決封裝相關品質與生產問題經驗 3.了解先進IC封裝技術/材料開發流程, 包含bumping/Fan-out/WLCSP/2.5D/3D/CPO 封裝 4. 熟悉不同封裝結構技術,包含PBGA/TFBGA/FC/PoP/PiP/SiP/InFO/CoWoS
1. 固定資產帳務處理及管理，年度盤點規劃 2. 各類所得扣繳申報作業 3. 會計師查帳及主管機關資料準備提供 4. 協助主管交辦事項及其他例行性事項 職缺需求 1. 四年以上工作經驗 2. 財務會計相關 3. 熟悉SAP系統
設計測試硬體配件 IC驗證 CP/FT 測試程式開發 量產維護 職缺需求 四年以上測試經驗 具備CP/FT 程式開發能力 熟悉V93K or Uflex 機台
1. 開發與制訂射頻（RF）電路系統架構及其規格。 2. 開發與驗證射頻相關之校正（calibration）與控制演算法。 3. 制訂射頻前端元件（RF front-end components）規格，並最佳化完整的射頻/基頻鏈路預算（link budget）。 職缺需求 【基本條件】 1. 具備射頻（RF）電路架構規劃與設計的經驗。 2. 具備紮實的通訊系統知識。 3. 精通 MATLAB、ADS 與 SystemVue 等 EDA（電子設計自動化）軟體工具。 4. 熟悉 Wi-Fi、藍牙（Bluetooth）、LTE、NR（5G 新無線電）或其他相關通訊標準。 【加分條件】（具備以下條件尤佳） 1. 精通 C、C++ 與 Python 程式語言。 2. 了解蜂巢式網路（Cellular）或 Wi-Fi 系統的數位基頻前端（Digital baseband front-end）設計原理。 3. 具備前端（FE，Front-End）電路量測的實務經驗。
與架構師及跨團隊協作，理解GPU規格並制定驗證策略。 使用SystemVerilog/UVM開發測試框架與協同模擬環境，進行GPU邏輯單元、子系統及頂層驗證。 制定並執行驗證測試計畫，注重功能覆蓋率。 生成隨機及定向測試序列，維護測試平台、計分板、BFM及回歸測試。 進行RTL與覆蓋率分析，優化測試場景，修復潛在漏洞。 支持性能驗證、模擬、數據收集、調試，以及PPA優化。 執行正式驗證 職缺需求 計算機、電子、計算機工程或相關專業碩士／博士學位或同等學歷 5年以上ASIC設計驗證經驗 熟練掌握測試規劃、SystemVerilog/UVM、受約束隨機、功能覆蓋、協同模擬、腳本編寫 優秀的問題解決、調試及根因分析能力 具備計算機架構和GPU流水線的實際經驗 良好的團隊協作能力及優秀的口頭與書面溝通能力 能適應快速變化及多地協作的工作環境 優先條件：具備GPU著色器子系統及GPU架構相關經驗
我們正在招募才華橫溢的工程師，加入我們的 GPU 架構團隊。在此職位上，您將站在最前沿，參與定義下一代行動高效能 GPU。您將負責開發一套基於 C++ 的模型，該模型將作為晶片流片前進行架構探索、瓶頸分析及效能預測的核心工具。 無論您是熱衷於電腦架構的應屆畢業生，還是在效能建模領域深耕多年的資深專家，我們都誠摯邀請您加入我們，共同突破圖形渲染與運算效率的極限。 職缺需求 擁有電腦科學（CS）、電機工程（EE）或相關領域的學士、碩士或博士學位。 • 精通 C++ 語言（C++17/20），並對資料結構、演算法及物件導向（OOP）設計模式有深入研究。 • 對電腦體系結構（包括管線、快取一致性、儲存層次結構及亂序執行）有紮實的理解。 • 熟練腳本語言（如 Python、Bash），並能運用於自動化任務及資料分析。 • 具備優秀的分析能力，並秉持著數據驅動的思維模式。 • AI 效率：精通利用 AI 程式設計助手，專注於有效率且精準地運用此類工具，以達到生產力最大化。
我們正在尋找一位技術精湛的相機ISP演算法開發工程師加入我們的團隊， 理想的候選人將負責設計、開發和優化相機系統的影像信號處理（ISP）演算法， 主要職責包括開發演算法提升影像質量、減少噪聲和改善色彩準確性。 候選人應具備影像處理、電腦視覺的強大背景，並熟練掌握C/C++和Python等編程語言， 具有相機硬體和實時處理經驗者優先。 加入我們，一起創新，推動相機技術的極限！ 職缺需求 1. 熟悉影像處理演算法 2. 熟悉電腦視覺演算法 3. 熟悉相機功能及演算法 4. 熟悉訊號處理 5. 熟悉 Python, C/C++ 語言程式設計
負責電腦視覺演算法開發，包括影像處理、深度學習、機器學習以及影像識別。 這些技術將應用於相機相關產品，涵蓋多個產品線 (如：ISP, Auto Exposure, Auto Focus, Auto White Balance, HDR image processing, AI-ISP)。 職缺需求 1. 影像處理, 深度學習, 機器學習, 影像識別, 電腦視覺演算法開發 2. 熟悉Python, C/C++, 系統架構設計 & 性能分析 3. 熟悉agentic AI平台及技術 (如Claude Code, agent skill, ...)
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