1. Define the roadmap and product portfolio of tablet, eReader, OTT, smart display and wearable. Drive product positioning and value propositions. 2. GTM strategy planning and execution, win design awards, and deliver revenue. 3. Customer engagement and relationship build up. 4. Collaborate closely with internal RD, PM team to understand product architecture, roadmap, and differentiating features, ensuring marketing deliverables are technically accurate. 5. Work with sales teams to support customer engagements, respond to technical inquiries, and drive product adoption. 職缺需求 1. Major in EE/CS related with at least 8 years of experience in the semiconductor industry. 2. Strong understanding of hardware/software integration, SoC platforms, system view, AI/ML, cloud/edge compute. 3. A deep and nuanced understanding of multimedia products, with an ability to grasp and leverage the latest technological advancements. 4. Ability to manage multiple product lines and define different promotion strategy. 5. Good customer engagement ability and communication skills to simplify technical concepts for different audiences.
1. Own the top-level integration of internal and third-party IPs into SOC or FPGA platform. 2. Ensure interface compatibility, clock/reset domain correctness. Resolve integration issues including timing, CDC/RDC, and floorplan. 3. Work closely with architect to define specification, support physical design team through synthesis constraints and integration guidance, partner with firmware and validation teams to ensure smooth bring-up and validation. 職缺需求 1. Master's degree in Electrical Engineering, Computer Engineering, or a related field. 2. 5+ years of experience of hands-on experience in ASIC/SOC design with strong proficiency in RTL design. 3. Experience with EDA tools for synthesis, lint, CDC, simulation, and debug. 4. Experience with high speed interface and DRAM controller are preferred.
1. Develop Ethernet MAC for HPC networking applications. 2. Work closely with architecture, verification and physical teams from specification to implementation. 職缺需求 1. Master's degree in Electical Engineering, Computer Engineering, or a related field. 2. 5+ years of experience of digital design with a strong record in Ethernet MAC or network protocol implentation. 3. Familiarity with Ethernet standard specifications. 4. Familiarity with industry-standard interfaces like XGMII. 5. Experience with emerging interconnect specifications such as UALink or UEC standards is highly valued.
We are looking for a highly experienced PISI Technical Leader to join our team. The ideal candidate will have extensive experience in Power Integrity and Signal Integrity, with a strong background in high-speed IO interface simulations and PDN analysis. As a PISI Technical Leader, you will guide customers through Signal Integrity and Power Integrity signoff, model and optimize system components, and collaborate with various teams to ensure optimal package, PCB, die, interposer, and substrate designs. 1. Guide customers to complete Signal Integrity and Power Integrity signoff. 2. Model and optimize vias, connectors, sockets, breakouts, and various system components using commercial tools. 3. Perform system-level signal integrity simulation in high-speed IOs such as PCIe, SerDes 4. Architect and simulate power delivery systems, including multiple dies, substrate, interposer, PCBs, and on-die PDN models. 5. Collaborate with multiple teams, including layout, design, and customers, to optimize package, PCB, die, interposer, and substrate designs. 職缺需求 1. 10+ years of Power/Signal Integrity related experience. 2. Experience with high-speed IO interface simulations, including SerDes, PCIe 3. Experience with PDN analysis and simulation.
Job Description: MediaTek Inc. (MTK) is a global fabless IC design company based in Hsinchu, Taiwan. As a production planner at MTK, you will independently develop production plans for the product lines you are responsible for, and execute these plans to ensure supply targets are met through cross-functional collaboration, both internally and externally. You’ll need to: Develop inventory strategies and capacity preparation plans. Communicate plans and strategies with the BU and sales teams to finalize a feasible plan. Execute your plans, monitor and track capacity ramp-up status, and resolve any issues that arise. Monitor production progress and address any issues as needed. Ensure production schedules are met to fulfill customer demands. 職缺需求 Minimum qualifications: BA/BS degree or equivalent practical experience. At least 2 years of experience in supply chain management. Preferred qualifications: Relevant experience in the semiconductor industry (foundry, assembly, testing). Demonstrated experience collaborating and working cross-functionally with sales, engineering, operations, and subcontractors. Proficiency with ERP systems, SCP systems, spreadsheets, and presentation software. Detail-oriented with strong execution skills. Excellent written and verbal communication skills.
我們正在尋找在半導體設計實現 (semiconductor design enablement) 領域具備深厚背景的專家，主要負責先進製程與封裝 (如 3DIC, CoWoS) 的 PDK 開發及 RC 萃取開發。 職缺需求 1.PDK 開發 (PDK Development): 具備使用 Cadence 或 Synopsys 平台為先進製程或封裝技術開發、維護及驗證工藝設計套件 (PDK) 的實務經驗。 2.實體驗證 (Physical Verification): 精通實體驗證規則檔 (rule decks) 的撰寫與除錯，包含 DRC (設計規則檢查)、LVS (電路佈局驗證)、PERC (可程式化電氣規則檢查) 及 LPE (佈局寄生參數萃取)。 3.RC 萃取方法學 (RC Extraction Methodology): 具備領導複雜實體設計的 RC 萃取流程之開發、優化與驗證的實證經驗。 4.先進封裝實現 (Advanced Package Enablement): 具備異質整合 (heterogeneous integration) 與先進封裝技術的知識和經驗，例如 3DIC、CoWoS 或 CPO。 5.佈局與繞線技術 (Place & Route Technology): 具備為數位實作流程開發與維護佈局與繞線 (P&R) 技術檔案 (TechFiles) 的經驗。 6.協作能力 (Collaborative Skills): 具備出色的溝通與團隊合作技巧，並有與晶圓代工廠 (foundries)、EDA 供應商及內部設計團隊高效合作的成功經驗。 7.加分條件 (Preferred Qualifications): -熟悉 3DIC、CoWoS 的 PDK 或技術檔案開發。 -熟悉 EDA 工具、Cadence SKILL、Tcl、Python 或其他腳本語言 (script) 的程式設計。 -熟悉靜態時序分析 (STA)。 -熟悉效能指標 (FOM) 分析及其在設計與技術協同最佳化 (DTCO) 的應用。
What Makes Us Different MediaTek is one of the world's top five IC design house, offering comprehensive and diverse training programs that enable you to collaborate with top engineers on world-leading products. With a global presence, you can experience international collaboration. Additionally, MediaTek provides competitive salary and benefits packages to ensure a rewarding work experience. Here at MediaTek, tomorrow is built by you. 【Job Description】 Seeking a Patent Engineer to manage global patent applications, provide consultation to personnel on patent matters, and actively engage in invention disclosures. The role involves executing, leading, and analyzing patent search results, providing recommendations on validity and non-infringement, and overseeing the progress of patent reviews, reexaminations, and litigations. 職缺需求 • B.S. degree in telecommunications related or IC related engineering disciplines, graduate degrees preferred • 3 years minimum of patent prosecution and management experience gained in-house or in a law firm • Working fluency in English and excellent communication skills are musts • Experience in supporting IP litigations would be a plus
1.CPO SERDES 系統開發 2.CPO Optical 系統開發 職缺需求 1.具備高速SerDes(100Gbps+、PCIe Gen6) 系統驗證及問題分析與量產經驗尤佳 2.熟悉高速SerDes及光通道相關測試儀器儀器者尤佳（ex. PPG、BERT、real-time/sampling Scope、VNA等） 3. 有光模組,光電開發經驗尤佳. 4. 熟悉 C, Python, C# and embedded system, matlab 5. 自發性及學習力強、良好的溝通能力及團隊合作經驗 6. 具備英文口說與讀寫能力
1. 產品品質問題電性 / 物性分析 2. 產品測試機台操作和測試分析 3. 跨部門溝通以分析產品故障真因 職缺需求 1. 兩年以上半導體領域工作經驗 2. 碩畢, 電機電子或相關科系 3.須具備產品故障分析與測試實務經驗 4.具備可測試性電路設計(DFT)的經驗尤佳
1. Processor core, cache and peripheral verification 2. Verification flow and methodology 3. Advanced tool and verification technology survey 職缺需求 1. Experienced in design verification, familiar with SystemVerilog/UVM 2. DSP/CPU design or verification is a plus 3. Low power verification , UPF/MVSIM/NLP is a plus 4. CDC verification is a plus 5. Function safety related experience is a plus
1. 5G NR通訊系統分析 (a) 5G NR實體層規格及流程驗證 (b) 基頻演算法設計驗證及訊號分析 (c) 整體系統效能驗證與流程分析 2. 5G NR通訊平台開發 (a) 內部測試平台開發 (基本功能,算法) (b) 系統性能以及RRM分析平台開發 職缺需求 1. 具無線通訊,數位通訊,數位訊號處理等相關背景尤佳 2.熟悉OFDM相關系統 (如NR, LTE, WiFi)尤佳 3. 有研讀過3GPP NR/LTE Spec或相關演算法設計分析經驗者佳 4. 有Protocol (L2/L3/L4)相關經驗佳
• 負責高速SerDes的開發，包括韌體設計與演算法實現、IC功能驗證、系統效能優化以及客戶支援（熟悉架構、韌體、除錯、優化及測試相關工作） • 開發自動化驗證（使用C++、Python、C#和MATLAB） • 與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產 職缺需求 1.碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制、相關科系畢業為主. 2. 熟悉 C, Python, C# and embedded system, matlab 3. 具備以下其中一項知識或經驗者尤佳： 乙太網路、 高速SerDes相關技術、SI/PI（訊號完整性/電源完整性）知識。 4.具備以下其中一項經驗者尤佳：演算法實現、韌體驅動程式設計、自動化測試開發 5. 熟悉高速SerDes相關測試儀器者尤佳（如PPG、BERT、示波器、Scope、VNA等） 6. 具備30Gbps以上SerDes相關經驗者（如56G/112G乙太網路SERDES、Fibre Channel、PCIe Gen6、USB 4.0） 7. 自發性及學習力強、良好的溝通能力及團隊合作經驗 8. 具備英文口說與讀寫能力
負責PCIe MAC/PHY系統開發，包括軟體/韌體設計、IC功能驗證、系統效能優化、軟體驅動程式/SDK及客戶支援（熟悉架構、軟韌體、除錯、優化及測試相關工作） •開發PCIe Linux或嵌入式作業系統驅動程式 • 開發自動化驗證（使用C, C++, Python） •與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產 職缺需求 1.碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制、相關科系畢業為主. 2. 熟悉 C, Python and embedded system 3. 具備PCIe於Linux/Windows作業系統驅動程式開發經驗者尤佳 7. 自發性及學習力強、良好的溝通能力及團隊合作經驗 8. 具備英文口說與讀寫能力
1. Burn in process flow set up & qualification plan 2. Qualification failure electrical & physical analysis 3. Product reliability concern engagement with customer 4. New test supplier audit & qualification 5. Testing house supplier quality & reliability management (Quality incident handling, PCN, regular audit, score card, etc.) 6. New product/technology introduction quality & reliability management 7. Testing house supplier quality improvement project 職缺需求 1. MS degree (or above) in Science or Engineering. 2.Familiar with Testing process flow. 3. Familiar with problem solving and 8D CAR methodology 4. VQA/IQA or MQR related experience 5. Burn in set up and operation experience
1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development 3. Common strip format unification management 4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) 5. PCB technology development and DRM owner 職缺需求 1. New SBT vendor bring up , New SBT vendor YIP , troubleshooting and Ops 2. 3D, 3.5D & e-IVR Technology Enabling, CPC/CPO technology building block development 3. Common strip format unification management 4. Advanced PCB Ultra-Large size. I.e., CoWoP, DCAI PCB w/ high layer counts (PCB vendor ISU, GCE, UMTC, VGT ) 5. PCB technology development and DRM owner
•重點開發技術: 系統軟韌體開發、高速資料實體層(physical layer) 資料傳輸軟體開發、優化硬體效能及產品量產品質控管 •主要目標: 完成Enterprise/AI/xPU等相關產業客製化IC的軟韌體開發與系統整合，並協助客戶產品量產 •負責新產品的系統設計與開發，確保符合公司及客戶的需求 •協助量產過程中的技術問題解決，並提供專業建議以提升生產效率與品質 •與跨部門團隊合作，確保產品從設計到量產的順利過渡 •分析並改善現有系統和流程，以提高產品質量和生產效率 •參與產品測試和驗證，確保產品符合相關標準和規範 職缺需求 •電機工程、電信工程、通訊工程、控制工程、電腦科學或相關領域的碩士以上學位 •熟悉AI/xPU的測試與量產流程，具備問題排除與實際量產的經驗 •具備跨Team合作的溝通與整合能力，包含計畫規劃與執行 •至少4年以上系統設計與量產相關工作經驗，並熟悉電子產品的開發流程及量產技術 •具備良好的問題解決能力和溝通技巧 •精通 C、Python、C#、嵌入式系統和 MATLAB。 •具備以下至少一項經驗： 計算機結構與原理、嵌入式系統/電腦作業系統、通訊原理/數位訊號處理/演算法開發及高速訊號及SI/PI觀念
1. 負責晶片間（D2D & UCIe ) PHY IP硬體驗證與軟體開發。 2. 主導相關IP開發，熟悉ASIC專案中的軟體/SDK，能夠進行問題調試、最佳化和測試。 3. 與團隊合作，完成功能/系統啟動、驗證、效能最佳化和調整。 4. 實現產品設計導入，並支援產品量產。 職缺需求 1. 碩士以上; 電機工程、電信工程、通訊工程、電控工程、電子工程、資訊工程、自動控制相關科系畢業。 2. 擁有3年工作經驗者優先，尤其是在晶片間（D2D & UCIe）實體層和ASIC產品方面。 3. 精通Python、C、C++和MATLAB。 4. 能夠分析測量PLL訊號，尤其熟悉D2D物理層驗證方法。 5. 自發性及學習力強、良好的溝通能力及團隊合作經驗。 6. 具備英文口說與讀寫能力。
我們正在尋找一位同時精通 AI 與晶片設計的專家，能夠將人工智慧技術應用於晶片設計流程，提升生產力與產品品質。此職位需要具備 IC 設計知識，以及機器學習／生成式 AI 的專業能力，能夠主動發掘並定義創新機會，設計可行且穩定的解決方案，並優化設計流程。若您對晶片設計流程優化及數位 IC 設計有相關經驗，將會是加分項目。 我們歡迎對跨領域創新充滿熱情、喜歡處理複雜資料並挖掘洞見、勇於挑戰的工程師或資料科學家加入我們的小型多元團隊。您將透過快速迭代，為 MediaTek 的晶片設計流程提供最合適的 AI 解決方案。 軟實力方面，您需具備主動積極的態度、持續學習與適應新知的能力、優秀的溝通技巧，以及跨部門協作的能力。硬實力方面，您需擁有扎實的程式設計能力，並具備足夠的 IC 設計與 AI 技術知識。 職缺需求 1. 熟悉機器學習、深度學習或生成式AI技術，能應用於晶片設計流程。 2. 具備良好的程式設計能力，熟悉Python、C++或相關語言。 3. 能夠分析複雜資料，發掘流程優化或自動化的機會。 4. 具備跨部門溝通與協作能力，能與設計、製程及AI團隊合作。 5. 具備主動學習與解決問題的能力，樂於接受新挑戰。 6. 具備良好的中英文口語與書面表達能力。 7. 有晶片設計流程優化及數位 IC 設計相關經驗。 8. 具備AI模型部署、驗證或優化經驗者加分。 9. 具備專案管理或快速原型開發經驗者優先考慮。
1. Develop 3.5D methodology from RTL to GDS and Package 2. Coordinate Thermal and PI/SI team to deal with high power design 3. Execute the project at different phases 職缺需求 1. Advance process or package design experience 2. Better to have 3.5D design experience 3. Better to have experiene in large scale and high power design 4. Good communication skill in English
1. Develop Playbook for ASIC design 2. Monitor the project execution based on the Playbook 3. Coordinate among different teams to improve Playbook 職缺需求 1. ASIC Project implementation from RTL through tpeout to production 2. Program management for a complex project 3. Good communication with external customers and internal project teams
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