•Leading and integrate team members and technology of analog IP to engage new SOC products including multi-vertical product lines •Work as analog project management team and work closely with SoC Integration teams responsible for enabling on-time silicon to meet product schedules Multi-task skills will be key to lead several tasks of project at a time •Track and drive resolution of technical issues between multi-functional teams including Design, Verification, Validation, Process Technology, Packaging, Quality and Reliability, System Hardware and Application •Convert data into a clear story to communicate to partners and organizations at all levels. Also, as good communication bridge between Analog and SOC •Regular project status presentations for executive leadership review including issue report, bug tracking, risk assessment and mitigation plan 職缺需求 •2+ years of technical Program or Project Management or 4+ years in analog IP design experience •With experience of leading a full Mixed Signal design flow, from concept to delivery •Advanced knowledge of analog IP development, tools/flows, design methodologies and development flow of SoC •Command of hardware and software integration challenges •Committed to owning/driving project development using well-defined metrics •Excellent written and verbal interpersonal skills in Chinese and TOEIC score >600 •Excellent communicator and teammate with the ability to work effectively with teams with dynamic strengths and abilities across multiple locations •Strong teammate and creative thinker able to lead technical teams and multi-functional groups against plans
This position involves developing memory architectures, creating circuit implementation techniques and be an interface with CAD team for full verification and model generation. You have opportunity to know how memory design can be implemented into all Mediatek products. 職缺需求 (1) MS or above with major in EE (2) 5+ years of professional experience designing embedded memories (3) SRAM/UHDTP/2P/DP/ROM architectures and advanced custom circuit implementations. Advanced technology nodes are a plus (4) Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler flow, timing characterization (5) Physical implementation and layout supervision (6) Proficient in English communication
類比、射頻、3D-IC矽中介層等電路全客製化佈局設計及自動化流程設計 職缺需求 * 學士或碩士 EE, CE, CS 等相關領域 * 至少 3 年以上相關3D-IC矽中介層或類比、射頻等電路佈局經驗 * 熟悉類比、射頻電路布局設計及驗證 * 熟悉電路布局EDA工具，如Virtuoso, Calibre, Laker, Custom Compiler, etc. * 具備先進FinFET製程的電路佈局經驗 * 具備程式能力設計自動化流程或APR經驗會是個加分項目 * 具備獨立作業及良好的團隊合作能力 * 英文溝通能力與全球團隊合作
Analog circuit design, including ADC, DAC, PLL, PGA, OPAMP and analog front end circuit design. 職缺需求 Master's degree or above
1. 先進封裝BGA基板佈線與佈線實體驗證 2. 2.5D IC (CoWoS_S; CoWoS_L; CoWoS_R; EMIB) RDL 與基板佈線與佈線實體驗證 3. 與封裝設計工程師合作完成封裝設計需求與目標 4. 新封裝佈線方式評估與開發 5. 新封裝佈線輔助設計軟體評估 職缺需求 1. 具大學或以上，電機，電子，機械或相關工程領域學歷 2. 熟悉Cadence APD/SiP or Siemens XPD PKG layout tools 並可獨立流暢操作設計軟體進行封裝設計佈局。 3. 熟悉封裝設計與 RDL/基版佈局流程 4. 熟悉FCCSP/FCBGA/HBPOP/PKG Module 相關封裝結構 5. 有CoWoS 結構與 Interposer/RDL/SBT design 相關經驗尤佳 6. 有Cadence APD skill 語言開發能力者尤佳 7. 熟悉封實體布局驗證 (DRC, LVS) 流程與相關軟體操作 (Calibre, 3DStack) 尤佳
• Integral part of Tier-1 OEMs team – communicate, manage and prospect long term business relationships with North American tier-1 OEMs, ODMs, hub service providers and internal cross functional teams to achieve revenue goal • Facilitate and track customer forecast, and execute sales operation activities including shipment notification, execution plan, documentation, RMA, etc. with customers and hub service providers • Influence and advocate for MediaTek based products and actively monitor customer growth, movement and market trend of PC/NB industries • Gain a solid understanding of the competitors’ activities and benchmarking • Clearly articulate MediaTek solution differentiation and value proposition associated • Ability to complete other assignments and special projects as requested 職缺需求 • > 8 years of working experience in semiconductor industries with related customer support, sales or account management experience. • Fluent spoken and written English with good communication and documentation skills • Proficiency in Microsoft Office and CRM software such as Salesforce.com. • Domestic and overseas business travels for customer visits required (~20%) • Self-motivated, proactive, details- oriented and a team player • Located in Hsinchu, Taiwan
1. 各種產品類型之封裝設計及規畫。 2. BGA substrate設計及佈局。 3. 與封裝廠合作，完成封裝圖面設計。 4. 先進封裝技術之開發。 5. 封裝設計平台之開發。 職缺需求 1.國立機械/電子/電機工程相關研究所(含)以上畢，精通英文。 2.熟悉 Cadence Allegro Package Designer, Autocad佳。 3.熟悉各種類型之封裝及基板設計流程及製程佳。 4.熟悉各種封裝結構如PBGA/TFBGA/FlipChip/POP/PiP/SiP/Module/Fanout佳。 5.熟悉Cadence APD skill language尤佳。 6.熟悉程式語言尤佳。 7.熟悉Chip design tool如Laker, Virtuoso 尤佳。
The candidate will design, supervise layout, help characterize transceiver front-end circuits for WiFi and Bluetooth production. 職缺需求 The ideal candidate would have an excellent track record in RFIC design and verification. 1. MS or PhD degree in Electrical and Electronics Engineering or equivalent. 2. Strong analytical skill is important for this position. 3. Hands-on transceiver building block design experience (e.g., LNA, mixer, TIA, analog filer; generic building blocks such as regulators, bandgap reference, current bias and voltage source). 4. Solid understanding of highly scaled CMOS process and device characteristics, and scaling-related impact to circuit design. 5. EM knowledge and EM tool usage, design experience in 28nm CMOS or beyond are important plus.
1. 無線 RFIC 類比電路設計. 2. 頻率合成器, 鎖相迴路, 壓控振盪器, 晶體振盪器, 除頻器 設計. 職缺需求 1. 碩士以上, 電機電子通訊相關科系畢業 2. 熟悉頻率合成器和鎖相迴路工作原理 3. 良好工作態度和溝通技巧
協助電源管理晶片規格製定, 新 IP 開發規劃及產品驗証協助類比晶片IP開發, 驗証. 職缺需求 類比或電源管理晶片驗証2年以上經驗
In charge of engineers/specialists and entry to middle level manager recruitment, R&R includes building partnership with hiring managers, talent sourcing and management, selection & interview, securing on-boarding and expand talent network. 職缺需求 1. At least 2+ years working experiences in recruiting. 2. Proficient in behavior interview skill and provide interview feedback for hiring decision making with hiring managers 3. Familiar with multi sourcing channels. Be able to partner with hiring managers to propose the best sourcing portfolio and effectively follow-up to fulfill talent requirements. 4. Proficient in using Microsoft Office software to integrate data and present the valuable information and insights. 5. Scoring over 800 in TOEIC or similar level in other language tests within two years
We are looking for a Senior DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality. Key Responsibilities • Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage. • Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation. • Perform ATPG, fault simulation, and coverage analysis. • Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode. • Lead silicon bring-up and debug of test features; conduct failure and yield analysis. • Work with product teams to facilitate pattern generation, validation, and DPPM improvement. 職缺需求 • Experience: 3+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC. • Tools: Practical experience with DFT EDA tools (such as Tessent, TestMAX) including scan insertion, ATPG, MBIST, boundary scan, and coverage debug. • Knowledge: Familiarity with RTL and gate-level integration of DFT features.Working knowledge of test strategies, coverage analysis, and fault simulation.Experience with memory BIST, boundary scan, JTAG/IJTAG, and system test concepts • Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field. Preferred Qualifications • Experience with advanced technology nodes (< 7nm). • Strong collaboration skills for working with cross-functional and global teams. • Excellent problem-solving skills to analyze CAD/DFT issues and implement solutions. Location: Hsinchu, Taipei, Singapore.
1. Develop and implement DRAM controller/PHY solutions for data-center applications. Validate functionality, improve design to optimize performance, power, latency and efficiency. 2. Memory controller/PHY Integration: Design and integration memory system. 職缺需求 1. Experience in designing and implementation of memory controller/PHY. 2. Familiar with the DRAM interface standards and memory technologies such as DDR or LPDDR or HBM. 3. Familiarity with DFI protocol of LPDDR or HBM. 4. Familiar with digital design and integration flow. 5. HBM controller/PHY IC design experience is a plus 6. Familiarity with AXI protocol
1. 負責制定產品技術目標, 財務目標與市占率目標, 並帶領團隊達到目標 2. 負責智能手機產品規劃,規格定義 以及財務評估 3. 負責產品生命週期內客戶推廣,項目導入,競爭分析以及應對規格 4. 分析智能手機市場,提出對應的商業規劃以及競爭策略 職缺需求 1. 有完整的 SoC 產品規劃經驗, 在 IC產品規劃經歷 至少 5年 2. 手機產業 相關經驗 3年以上 3. 具財務分析與市場分析能力 4. 具策略思考能力, 有完整的 產品 GTM 經驗 5. 中英文流利 能用英文做完整的產品介紹
1. Modem and AP SOC 產品規劃, 市場分析與技術可行性評估. 2. 產品上市規劃與行銷. 3. 全球Tier-one客戶商務合作與專案執行. 職缺需求 1. 具備成功記錄的SOC產品規劃經驗。 2. 具備技術可行性評估及專案量產的專案協調/領導經驗。 3. 產品和商務規劃的成功案例。 4. 掌握市場動態和趨勢的方法。 5. 與全球一級客戶合作的經驗。
1. Mobile gaming and GPU technology planning, marketing and design-in for Smart Phone Product. 2. Customer relationship management. 3. Market & competition analysis. 職缺需求 1. Master degree holder with major in electrical engineering, computer science, business or related fields 2. Familiar with GPU technology and ecosystem. 3. Familiar with Game technology and ecosystem. 4. Identifying the GPU’s target positioning, values, and selling points for smart phone market. 5. Identifying the game’s target positioning, values, and selling points for smart phone market. 6. Engaging with Google and Khronos events and planning. 7. Creating brand identity around game technology for smart phone market. 8. 6+ years of graphics engineering experience. 9. Over 2 years of experience of marketing consumer electronics product, or customer project management is a plus 10. Fluent English is a must
1. 高速Serdes系統技術開發(200Gbps+), 包括電通訊與光通訊(optical interconnect) 2. 定義系統技術規格並與設計團隊(Analog, Digital, Algorithm)討論系統架構, 建立模型模擬評估 3. Serdes 關鍵技術評估與開發( e.g., Next Gen Serdes, optical nonlinearity compensation, CPO technology) 4. 協助Serdes IP驗證問題分析 職缺需求 1. 碩士以上; 電機工程、電信工程、通訊工程、電控工程、電子工程、資訊工程、自動控制、相關科系畢業為主. 2. 熟悉 C, Python, C# and embedded system, matlab 3. 具備高速SerDes 、系統驗證、量產經驗、 SIPI、光模組相關經驗尤佳 4. 自發性及學習力強、良好的溝通能力及團隊合作經驗 5. 具備英文口說與讀寫能力
1. 在AI產品上負責Memory IP上相關開發、熟悉軟/韌體、除錯、優化及測試等工作項目。 2. 負責IP SDK 與診斷程式開發。 3. 協同團隊共同完成系統雛型建立、驗證及性能優化與調適。 4. 達成客戶端產品導入，並支援產品量產工作。 職缺需求 1. 碩士以上；電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制等相關科系畢業為主。 2. 3年以上有LPDDR4/DDR4 or HBM相關經驗尤佳。 3. 熟悉 C、Python、C++，and embedded system。 4. 具備分析與PHY訊號量測。 5. 熟悉AXI/AHB/APB protocols尤佳。 6. 自發性及學習力強、良好的溝通能力及團隊合作經驗。 7. 具備英文口說與讀寫能力。
• 負責高速SerDes的開發，包括韌體設計與演算法實現、IC功能驗證、系統效能優化以及客戶支援（熟悉架構、韌體、除錯、優化及測試相關工作） • 開發自動化驗證（使用C++、Python、C#和MATLAB） • 與類比/數位團隊合作，從原型設計到量產共同開發晶片 •協助客戶設計導入並支援量產 職缺需求 1.碩士以上; 電機工程、電信工程、電控工程、電子工程、資訊工程、資訊科學、自動控制、相關科系畢業為主. 2. 熟悉 C, Python, C# and embedded system, matlab 3. 具備以下其中一項知識或經驗者尤佳： 乙太網路、 高速SerDes相關技術、SI/PI（訊號完整性/電源完整性）知識。 4.具備以下其中一項經驗者尤佳：演算法實現、韌體驅動程式設計、自動化測試開發 5. 熟悉高速SerDes相關測試儀器者尤佳（如PPG、BERT、示波器、Scope、VNA等） 6. 具備30Gbps以上SerDes相關經驗者（如56G/112G乙太網路SERDES、Fibre Channel、PCIe Gen6、USB 4.0） 7. 自發性及學習力強、良好的溝通能力及團隊合作經驗 8. 具備英文口說與讀寫能力
- Lead and manage RFI/RFQ/SOW processes and negotiate commercial terms with AI data center clients, ensuring timely and accurate responses. - Collaborate closely with engineering, sales, and marketing teams to deliver data center ASIC solutions tailored for AI workloads. - Develop compelling product positioning and messaging for both internal and external stakeholders. - Work with field teams to assess competitive landscape and maintain market intelligence. - Support business development activities to the sales team to foster strong customer relationships. - Drive cross-functional teams to align on product specifications, timelines, and deliverables. - Prepare and present detailed product proposals and reports to executive leadership and customers. - PLM (Product Lifecycle Management), manage program from kickoff, execution, NPI all the way to volume production 職缺需求 - Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field; MBA is a plus. - 5+ years of experience in product management or technical marketing, preferably in semiconductor, IC design, or cloud/AI data center space. - Deep understanding of AI data center workloads, ASIC architectures, and accelerator technologies. - Experience engaging with hyperscale's, especially on custom ASIC projects. - Proven track record managing complex RFQs and technical requirements in a B2B environment. - Strong cross-functional leadership, communication, and negotiation skills. - Ability to translate market/customer needs into actionable product specifications. - Familiarity with server, networking, and storage technologies for large-scale cloud deployments. - Fluent in English (spoken and written); - Willingness to travel occasionally for customer meetings and industry events.
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